1. Field of the Invention
The present invention relates to interface circuits and more particularly to an interface circuit for providing a set and reset pulse to an Integrated Injection Logic (I.sup.2 L) latch circuit in response to an analog signal provided thereto.
2. Description of the Prior Art
There are many interface circuit applications requiring ramping capacitor time generators for supplying digital output signals therefrom. An example for such an application is in electronic ignition systems. In some contemporary electronic ignition systems, in response to a timing signals generated in timed relationship to the operation of the engine, there is provided a series of firing command signals for creating spark to operate the engine. The ignition systems usually require at least one and usually more than one capacitor to be ramped up and down, as understood, to generate the aforementioned firing command signals. For example, U.S. Pat. No. 4,041,912 to Charles Session, assigned to Motorola Inc., shows the need of such ramping capacitors and ramping circuits. The ramping capacitor may be clamped at upper and lower voltage levels in order to derive a delayed, well defined rectangular square wave output which is utilized to generate the foregoing firing command signals. In an electronic ignition system incorporating the embodiment of the present invention, the upper and lower capacitor voltage clamp levels are utilized to drive an I.sup.2 L latch circuit for providing the aforementioned rectangular output square wave. However, I.sup.2 L latches generally do not have immunity to noise induced input signals thereto.
Thus, there is a need for an interface circuit responsive to capacitor upper and lower voltage clamp levels for providing inputs to an I.sup.2 L latch circuit while providing high noise immunity.